The Principal Design Engineer in Micron’s NVEG (Non‑Volatile Engineering Group) organization will own and evolve the timing-critical circuitry between the NAND array and page buffer. This role is for a designer who is equally strong in architecture, transistor-level implementation, and physical aware timing closure – and who can lead technical direction across teams to deliver robust, scalable datapath solutions. You will drive designs that directly impact throughput, timing margin, power and yield, partnering closely with page buffer, array device, clocking, physical design, test, and product teams.
Minimum Requirements
BS or MS in Electrical Engineering with 8+ years of relevant experience. Experience in physical design flows and optimization. Proven ownership of blocks from concept -> design -> layout -> signoff -> silicon correlation. Deep expertise in CMOS analog/mixed-signal circuit design and device physics fundamentals. High-speed datapath timing analysis experience.
Preferred Requirements
Direct experience in NAND datapath and/or DRAM datapath design. Wave-pipelining, self-timed, or pulse-latched pipeline design techniques. Redundancy/repair architecture experience in dense arrays.
Benefits
Paid Time Off, Continuous Learning, Wellness Programs, Stock Purchase Program, Health Insurance, Recognition.
Micron Technology
