Jobs in Japan
Explore hand-picked jobs in Japan for English speakers across tech, education, marketing, and more.
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Explore hand-picked jobs in Japan for English speakers across tech, education, marketing, and more.
Vetted companies only. Apply from overseas.
Micron TechnologyThe Principal Design Engineer in Micron’s NVEG organization contributes to the development of new memory products by assisting with the overall design, layout, and optimization of datapath circuits for NAND flash memory. This position will drive task forces and make strategic decisions on major datapath architectural changes influenced by new design specs such as higher speed/lower power. They will assess pros and cons of new architecture and drive all activities pertaining its implementation. The role will be expected to lead technical datapath design projects, directing the design planning, layout, and validation activities according to project timelines. Responsibilities include designing and optimizing TSV (Through-Silicon Via) interface circuits connecting memory die to logic die, including Rx/Tx circuits for internal TSV channels, impedance matching, and timing margin analysis; developing and characterizing TSV electrical models and defining circuit design constraints for the datapath interface; defining and implementing signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis; defining and implementing power integrity requirements using TSV for highly parallel IO and array operations; designing and verifying TSV-specific DFT (Design for Testability) circuits, including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic; interfacing with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath; developing and executing functional verification plans for the TSV interface and internal parallel bus, including full-chip circuit simulation and Verilog regression; designing and optimizing the wide internal parallel data bus spanning multiple arrays, channels, and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus; architecting the datapath from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface, managing parallelism across bank groups and banks; developing clocking and synchronization strategies for the highly parallel internal bus, including wave pipeline design, clock distribution, and skew management; implementing and optimizing column redundancy and lane repair schemes compatible with HBM-like highly parallel bus architecture; defining timing budgets and performing timing analysis across the full internal datapath under PVT variations; supporting post-silicon validation, debug, and correlation activities, identifying schematic edits and driving necessary tape-out revisions; collaborating with packaging and assembly teams to ensure TSV reliability constraints are met within the datapath floorplan; communicating with project integration and other functional teams in design on specifications of major block interfaces; communicating with PE to drive silicon experiments and propose fixes and improvements for yield improvement and silicon debugging; communicating with Apps regarding introduction of new specs and limitations based on design requirements and limitations; and documenting and reviewing final results with experts and stakeholders.
- BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND or other high-density memory technologies. - Experience with TSV (Through-Silicon Via) interface circuit design or high-speed memory interface design (NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity. - Advanced knowledge and understanding of highly parallel bus performance, power and area optimization including clock distribution and skew management across wide data paths, and EpB (Energy per Bit) optimization in the context of 3D-stacked memory architectures. - Experience managing complex circuit design projects spanning multiple functional blocks and cross-functional teams, with the ability to effectively communicate design trade-offs, schedule progress, and technical outcomes to both design and non-design stakeholders.
- Hands on experience in utilizing AI to improve quality of design and efficiency - Experience on chip level PDN optimization - Comprehensive understanding on CMOS device and device reliability - Comprehensive understanding on CMOS BSIM model and CMOS target for high speed IO operation - Experience with signal/power integrity, power delivery network design, physical design
- Employees get paid time off and are encouraged to use it - We provide world-class education opportunities, linking learners and educators from around the world - A variety of wellbeing programs to meet you where you are - Purchase Micron stock through our employee stock purchase program at a discount - A choice of medical, dental and vision plans are offered to team members - We promote and reward peer-to-peer recognition
