Jobs in Japan
Explore hand-picked jobs in Japan for English speakers across tech, education, marketing, and more.
Vetted companies only. Apply from overseas.
Jobs in Japan
Explore hand-picked jobs in Japan for English speakers across tech, education, marketing, and more.
Vetted companies only. Apply from overseas.
Micron TechnologyMicron’s Non-Volatile Engineering Group (NVEG) develops best-in-class NAND memory products in die size, performance, reliability and power. NVEG is embedding AI across the entire design flow, and we are looking for engineers who use AI daily and actively reshape engineering workflows around it. As a Principal Design Engineer on the NAND datapath team, you will lead architecture and design of the internal datapath between the page buffer and IO: wave-pipelined buses, flop-to-flop timing, FIFOs, dataline sensing, column repair and clocking. You will use AI daily to accelerate design, timing closure and verification, help bring STA-based semi-custom methodology into a simulation-only flow, and set technical direction as a recognized leader. Responsibilities include defining, designing and verifying internal datapath blocks such as page buffer-to-IO data buses, wave pipelines, FIFOs, SER/DES front ends and datapath clocking to meet bandwidth, timing and power targets. Architect and close wave-pipelined and flop-to-flop paths, including setup/hold, skew/jitter budgets, PVT delay tracking, and delay trims across PVT and aging. Design dataline sense amps and precharge/latch sensing, covering offset, Monte Carlo/high-sigma margin, coupling and IR drop. Design column repair, fuse/repair storage and redundancy muxing with no bandwidth or timing penalty, and verify all repair configurations with test, PE and FW. Use AI daily for RTL generation, scripting, and timing/waveform analysis; make specs and checklists AI-consumable and build agents that automate timing, Monte Carlo and repair-coverage checks. Lead the move from SPICE-only closure to a semi-custom flow with characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows. Drive floorplan, bus routing and RC-aware delay matching with layout, and correlate post-layout timing. Champion AI adoption and best practices, define interface specs with cross-functional teams, support silicon debug, and mentor engineers.
- BS/MS in EE or related field with 8+ years in memory datapath, SRAM or high-speed custom design. - Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin). - Experience in sense amp, dataline or SRAM read/write design, including Monte Carlo/high-sigma verification. - Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation. - Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts or agents) that improved productivity or design outcomes.
- NAND/DRAM/SRAM periphery experience: page buffer, column decoder, global data bus, or array-to-IO pipeline. - Memory repair and redundancy design, and its impact on yield, area, timing and test time. - Timing-adjustment techniques (delay trims, DLL/DCC, training) and aging effects (NBTI/HCI). - Building AI agents, LLM/RAG pipelines or ML models for IC design, verification or debug. - Advanced CMOS device physics, mismatch modeling (BSIM), and low-power techniques (clock/power gating, leakage). - Working knowledge of STA and semi-custom flows mixing custom and standard-cell logic.
- Employees get paid time off and are encouraged to use it. - We provide world-class education opportunities, linking learners and educators from around the world. - A variety of wellbeing programs to meet you where you are. - Purchase Micron stock through our employee stock purchase program at a discount. - A choice of medical, dental and vision plans are offered to team members. - We promote and reward peer-to-peer recognition.
