Engineering Jobs in Japan

[2WP] Advanced Rider Assistance Systems - Feature Developer

Design, implement, and optimize radar-based ARAS functions using modern C/C++. Develop scalable core platform software while adapting features to match the unique vehicle dynamics, chassis behavior, and styling constraints of global motorcycle OEMs. Perform functional evaluations, data collection and initial calibration on test motorcycles at our Nasushiobara Proving Ground (regular trips, ~3 hours from Yokohama office) and on public roads. Work closely with international feature development teams, system engineers, functional safety managers and application engineers throughout the V-model lifecycle. Develop Python-based test pipelines, simulation environments, and measurement scripts to process and analyze radar sensor recordings from bench and track tests. Contribute directly to life-saving motorcycle safety innovations experienced by riders around the world. Work with dedicated development motorcycles, closed proving grounds, and advanced rider dynamics training. Collaborate across borders with premium international motorcycle manufacturers from the worldwide headquarters of Bosch 2WP in Japan. Receive continuous professional training and work in cutting-edge development environments with competitive compensation and flexible hybrid working arrangements.

Externalengineeringml ai

AI and Cloud Solution Architect - BytePlus - Japan

BytePlus is the enterprise technology arm of ByteDance, providing Generative AI, multimodal models, AI agent solutions, and cloud infrastructure capabilities to businesses worldwide. In Japan, we work with leading enterprises across multiple industries to drive AI adoption from proof-of-concept (PoC) to scalable commercial deployment. Our goal is not only to demonstrate cutting-edge technology, but to help organizations create sustainable and measurable business value. Partner closely with the Japan regional Sales team to identify customer business challenges and technical requirements. Break down complex business problems into practical and scalable AI solutions. Lead technical demos, architecture discussions, RFI/RFP responses, and PoC design and delivery. Drive PoC-to-production conversion and ensure measurable business impact. Build technical credibility within customer organizations, from engineering teams to C-level executives. Participate in or lead the design and implementation of Generative AI applications, including LLMs, RAG systems, agent architectures, and multimodal solutions. Design and implement end-to-end system architectures, including model orchestration, knowledge base construction, vector database integration, API connectivity, and overall system integration. Evaluate system performance in real production environments (accuracy, latency, cost, scalability). Optimize prompt structures, inference workflows, and caching strategies to improve system stability and efficiency. Continuously refine solutions based on customer business KPIs. Act as the technical lead in customer engagements, supporting commercial discussions and technical negotiations. Collaborate with the Sales team to drive deal closure and contract execution. Support account expansion initiatives (upsell / cross-sell). Take ownership of both technical quality and commercial success of assigned projects. Build and maintain long-term trusted relationships with enterprise clients. Provide structured frontline feedback to Product and Engineering teams. Drive localization and optimization of products for the Japan market. Identify repeatable, industry-level AI solution patterns and support scalable adoption. Contribute to the development of industry solution frameworks and methodologies for Japan.

Externalengineeringsecurity

Transformation Success Engineer

As a Cortex Transformation Engineer, you are a critical part of the Global Transformation Practice, ensuring our enterprise customers undergo a flawless migration and security operations transformation to modern platforms. Operating within a synchronized global model, you will own the end-to-end customer transition lifecycle, compressed into a high-velocity sprint. You will combine deep technical engineering acumen with exceptional customer-facing delivery to execute data cutovers, lead immersive operational workshops, and demonstrate quantifiable business value to customer security leadership. Your impact includes executing technical migrations of customer environments from legacy to modern platforms; owning policy mappings, data retention configurations, API setups, and log ingestion validations against Palo Alto Networks "Golden Standard" design templates. You will bridge implementation and platform adoption by running practitioner-focused "Day in the Life" workshops, educating customer teams on native platform workflows, alert triage, incident response, Agentic-AI, and automated playbooks through 1-on-1 and cohort-based delivery. You will also lead structured Value Realization sessions with customer technical stakeholders, using native platform dashboards to demonstrate ROI, security efficacy, and operational efficiency and secure formal project sign-off and customer delight.

EN: BusinessJP: Not RequiredVisa: Not Available

Externalengineeringqa

Modem Systems Test Engineer - Wireless Technologies and Ecosystems

In this role, you will own the end-to-end test lifecycle for key cellular features across LTE, 5G NR, and future standards, while driving root-cause analysis on complex baseband software and firmware issues. You will also analyze incoming carrier specifications, map them into structured test plans, evaluate environment applicability, and execute verification on advanced lab equipment. Additionally, you will author test cases for internal testing and expand test automation frameworks—leveraging AI/ML where applicable—to maximize coverage and surface defects early in the development cycle, ensuring we deliver the best possible wireless experience to Apple customers worldwide. Test Design & System Verification: Define, develop, and execute system-level test plans evaluating 4G/5G and emerging standards across protocol control and user planes as well as physical-layer performance. Carrier Acceptance & Specification Engineering: Translate complex operator specifications—with emphasis on Japanese carriers—into actionable test plans aligned with Apple’s product roadmap, executing verification across network simulators, call boxes, and lab testbeds. Protocol Log Analysis & Root-Cause Triage: Analyze protocol traces, RF captures, and diagnostic logs to isolate baseband firmware and software defects, performance bottlenecks. Cross-Functional Driving & Issue Resolution: Partner closely with Baseband Software, Firmware, Systems Engineering, RF, Carrier Engineering, and Regulatory teams to reproduce issues, verify fixes, and drive 3GPP and carrier conformance. Test Automation, Tooling & AI/ML: Leverage AI/ML to develop custom tooling/dashboards/automation frameworks.

EN: BusinessJP: Not RequiredVisa: Available

Internship (Tokyo)

At ispace, we believe in empowering the next generation of innovators. Our internship program offers a unique opportunity to work alongside world-class engineers on real projects that contribute to our mission of expanding humanity’s presence in space. ispace interns work across teams in R&D/Engineering, Business, IT, Legal and Finance to tackle challenges, collaborate on solutions, and drive impactful change for our clients and users. Along the way, you’ll gain valuable skills and lay the foundation for your career. Our program is highly specialized—we do not offer “general internships.” Interns become an integral part of the team, working on actual projects and learning directly from experienced professionals. To succeed, candidates must possess the technical skills required for the role they apply for. Engineering roles include Design, Mission Operations, and Production/AIT. Various corporate roles are also available. Internships can start at any time and the length of the internship also varies. Part time internships are available, but our preference is for longer term (6 months or more) and full time. The position is based at the Tokyo office; remote internships are not available. English or Japanese language ability is mandatory.

Externalengineeringfullstack

Vice President

The Synthetic Product Group (SPG) business offers institutional clients and hedge funds products which are optimal with respect to tax, balance sheet and funding. Business revenues come from commissions, financing, and dividends through the trading of CFD and Equity Swap OTC instruments alongside futures, ETFs, and structured products. It is part of a front to back alignment where engineers are embedded with the revenue generating part of the business. This provides opportunities to partner closely across the SPG organization to deliver the firm even more effectively and efficiently to our clients. SPG engineering team is a dynamic and innovative front office team that partners directly with trading, sales, quants, operations, prime services, and other engineering teams across the globe. We focus on building and enhancing the applications and workflows that support the SPG business and our clients. As a key full-stack developer of the team, you will be at the forefront of various revenue-driven technology builds and working in a fast-paced changing environment. You may be working on a new business initiative to design the trade flow for the firm's synthetic product offerings. You may be building a cutting-edge technology stack that parallelizes the processing of contract lifecycle events with utilities to capture and visualize system performance. If you are interested in learning how the SPG business model works and how to apply your expertise to build the leading industry product to make great impact to the business, this position will be a great fit. With this role, you will be getting lots of exposure on understanding the business model/principles, as well as how to serve clients and the firm by using your business and technical expertise. You will have the opportunity to liaise with experts in business, engineering, and operations across the globe in an environment that encourages open discussion and is focused on the delivery of robust, reliable software. You will be participating in the full product lifecycle from requirements gathering, design, implementation, testing, support, and monitoring system performance. You’ll have access to the latest AI models and backing from the firm to leverage your AI expertise to drive efficiency and innovation. You will learn what the One Goldman Sachs concept is and how we work as a team. If you are looking for new challenges and opportunities, this is the role that you should apply and consider. Responsibilities include designing, building and maintaining high-performance, high-availability, high-capacity, yet nimble and adaptive platforms for risk hedging, trade execution, trade booking and workflow management as well as post-trade processing; designing and building solutions to enhance and scale up the infrastructure to support business growth and new products, in a holistic front-to-back approach; finding opportunities to apply AI as a force multiplier to both technical and business deliverables, contributing to the SPG AI toolkit and evangelizing AI within the organization; collecting data and metrics from existing systems to guide decision making and business intelligence, developing or enhancing tools as necessary to collect them; and communicating with traders, sales, strategists, operations, and compliance officers to gather new requirements, design workflow, deliver features and provide user support.

Staff Design Engineer

As a Sr. or Staff Design Engineer in the NVE Design Engineering Analog group at Micron Technology, Inc., you will contribute to the development of memory products that are best-in-class, using your specialized knowledge and Micron proprietary methods of designing and analyzing analog and mixed circuits used in the development of memory products. Responsibilities include designing, simulating, optimizing, and floor planning NAND circuits; evaluating design feasibility and analyzing circuit functionalities; implementing analog and mixed signal circuit design to meet specifications; validating design performance and functionalities by running block and chip level simulations using standard industry simulators; working closely with other functional teams to evaluate, analyze, and improve NAND power consumptions; collaborating productively with other team members; reviewing existing and generating new technical documentation; building and maintaining Python-based AI utilities that interface with EDA environments to accelerate design tasks such as environment setup, corner execution, regression runs, automated documentation, and intelligent/predictive design/layout techniques; and supporting groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to proactively design products to optimize manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

Senior in-Market Engineer

The GAIL (Get AI Live) program deploys engineers directly into strategic customer engagements to drive real AI adoption and measurable value realization. The GAIL Core Team is the permanent engine behind that program — the stable foundation of institutional knowledge, tooling ownership, and senior expertise that makes every engagement, and every rotating engineer, better than the last. As a Staff Software Engineer on the GAIL Core Team, you will own the hardest engagements, set the quality standard for the entire practice, and build the infrastructure that scales it. This is hands-on, customer-facing work — not theoreti

Semiconductor Principal Design Engineer

The Principal Design Engineer in Micron’s NVEG organization contributes to the development of new memory products by assisting with the overall design, layout, and optimization of datapath circuits for NAND flash memory. This position will drive task forces and make strategic decisions on major datapath architectural changes influenced by new design specs such as higher speed/lower power. They will assess pros and cons of new architecture and drive all activities pertaining its implementation. The role will be expected to lead technical datapath design projects, directing the design planning, layout, and validation activities according to project timelines. Responsibilities include designing and optimizing TSV (Through-Silicon Via) interface circuits connecting memory die to logic die, including Rx/Tx circuits for internal TSV channels, impedance matching, and timing margin analysis; developing and characterizing TSV electrical models and defining circuit design constraints for the datapath interface; defining and implementing signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis; defining and implementing power integrity requirements using TSV for highly parallel IO and array operations; designing and verifying TSV-specific DFT (Design for Testability) circuits, including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic; interfacing with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath; developing and executing functional verification plans for the TSV interface and internal parallel bus, including full-chip circuit simulation and Verilog regression; designing and optimizing the wide internal parallel data bus spanning multiple arrays, channels, and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus; architecting the datapath from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface, managing parallelism across bank groups and banks; developing clocking and synchronization strategies for the highly parallel internal bus, including wave pipeline design, clock distribution, and skew management; implementing and optimizing column redundancy and lane repair schemes compatible with HBM-like highly parallel bus architecture; defining timing budgets and performing timing analysis across the full internal datapath under PVT variations; supporting post-silicon validation, debug, and correlation activities, identifying schematic edits and driving necessary tape-out revisions; collaborating with packaging and assembly teams to ensure TSV reliability constraints are met within the datapath floorplan; communicating with project integration and other functional teams in design on specifications of major block interfaces; communicating with PE to drive silicon experiments and propose fixes and improvements for yield improvement and silicon debugging; communicating with Apps regarding introduction of new specs and limitations based on design requirements and limitations; and documenting and reviewing final results with experts and stakeholders.

Solutions Architect, Manufacturing

NVIDIA is a world leader in computer graphics, artificial intelligence, and accelerated computing. For over 25 years, NVIDIA has been at the forefront of research and engineering around the greatest advances in technology. Our history of innovation drives us to solve the world's hardest problems. We are now seeking a Solution Architect to support Japanese manufacturing companies adopt GPU-acceleration and AI for Chemical and Materials Science. The use of AI for discovering novel chemicals, materials, and formulations is a growing area in Industry and Academia. We need someone with domain knowledge and great communication skills to be a trusted technical advisor to our customers and work on exciting projects focused on Industrial High-Performance Computing (HPC) and AI for Chemistry and Materials Science. The role involves being a technical expert with vision on integrating NVIDIA GPU-accelerated tools and microservices such as ALCHEMI, PhysicsNemo, and CUDA-X libraries into Industrial HPC, Chemistry, Material Science, and Semiconductor Manufacturing workflows. Support the business development team in guiding the customer through the sales process for NVIDIA’s platform of GPU compute systems and acceleration software. Be responsible for the technical relationship and assist our customers and partners in developing innovative products using NVIDIA technologies. Dynamically engage with developers, scientific researchers, and data scientists to understand their goals, strategies, and technical needs, and help to define and deliver high-value solutions that meet these needs. Answer questions and provide mentorship – you will help them build their GPU compute infrastructure and get the most out of their investment. Document what you know, and guide others. This can vary from building targeted training for partners and other Solution Architects, to writing whitepapers, blogs, and wiki articles, to working through challenging problems with a partner on a whiteboard. Keep up-to-date on the latest techniques in AI for Chemistry and Materials Science, including atomistic simulation, machine learning interatomic potentials (MLIPs), graph neural networks (GNNs) for property prediction, and structural generative AI models.

EN: BusinessJP: Business